23 lines
378 B
Text
23 lines
378 B
Text
entity toggle_demo is
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port (
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clk_in : in std_logic; -- System Clock
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data_q : out std_logic -- Toggling Port
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);
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end entity toggle_demo;
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architecture RTL of toggle_demo is
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signal data : std_logic := '0';
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begin
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data_q <= data;
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data_proc : process (clk_in)
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begin
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if (rising_edge(clk_in)) then
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data <= not data;
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end if;
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end process;
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end architecture RTL;
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